AMD Preps Trinity-Based Athlon II and Sempron Processors

From X-bit Labs: Advanced Micro Devices has released processor product data sheet documents covering specifications of low-cost AMD Athlon II and AMD Sempron central processing units (CPUs) that belong to family 15h better known as Trinity. The new low-cost chips will support all the capabilities of the more advanced brethren, will have two or four cores and will lack integrated graphics processing units.

Just like the rest AMD family 15h "Trinity" microprocessors, the new AMD Athlon II X2/X4 as well as Sempron X2/X4 chips will support main architectural features of the Piledriver architecture, including support for new instructions like SSE4.1, SSE4.2, AES, FMA, FMA4, AVX, AVX 1.1, BMI and others. The chips will use the same module Piledriver architecture with two 128-bit FPUs as well as level-two cache shared between each two cores (or one module), advanced power management, integrated dual-channel DDR3 memory controller, PCI Express 2.0 x16 controller and so on, reports CPUWorld web-site.

AMD Athlon II X2 and X4 family 15h microprocessors will have one or two Piledriver modules (two or four x86 cores), 2MB of L2 cache per module (4MB per chip), dual-channel DDR3 memory controller with official support for up to 1866MHz clock-speeds for memory and will also support Turbo Core 3.0 dynamic acceleration technology. The central processing units will not be too different from the A-series accelerated processing units when it comes to x86 performance, but since it will not have integrated AMD Radeon graphics core, it will not be able to take advantage of GPU compute technologies that are gaining importance.

AMD Sempron family 15h central processing units will also will have one or two Piledriver modules (two or four x86 cores), 1MB of L2 cache per module (2MB per chip), dual-channel DDR3 memory controller with official support for up to 1600MHz clock-speeds for memory. Given the lack of integrated GPU, Sempron will also not be able to take advantage of heterogeneous computing.

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